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• W3148632407 abstract "Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SER) of combinational logic circuits. First, we propose a gate sizing algorithm that trades off SER reduction and area overhead. This approach first computes bounds on the maximum achievable SER reduction by resizing a gate. This bound is then used to prune the circuit graph, arriving at a smaller set of candidate gates on which we perform incremental sensitivity computations to determine the gates that are the largest contributors to circuit SER. Second, we propose a flipflop selection method that uses slack information at each primary output node to determine the flipflop configuration that produces maximum SER savings. This approach uses an enhanced flipflop library that contains flipflops of varying temporal masking ability. Third, we propose a unified, co-optimization approach combining flipflop selection with the gate sizing algorithm. The joint optimization algorithm produces larger SER reductions while incurring smaller circuit overhead than either technique taken in isolation. Experimental results on a variety of benchmarks show SER reductions of 7.9times with gate sizing, 6.6times with flipflop assignment, and 28.2times for the combined optimization approach, with no delay penalties and area overheads within 5-6%. The runtimes for the optimization algorithms are on the order of 1-3 minutes" @default.
• W3148632407 created "2021-04-13" @default.
• W3148632407 creator A5077144248 @default.
• W3148632407 creator A5089272490 @default.
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• W3148632407 date "2006-11-01" @default.
• W3148632407 modified "2023-09-27" @default.
• W3148632407 title "Soft Error Reduction in Combinational Logic Using Gate Resizing and Flipflop Selection" @default.
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• W3148632407 doi "https://doi.org/10.1109/iccad.2006.320165" @default.
• W3148632407 hasPublicationYear "2006" @default.
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