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- W3149260094 abstract "A 4-Mb (512 K*8) CMOS SRAM that uses a 0.5- mu m quadruple-poly double-metal CMOS technology to attain 23-ns address access time with a single 5-V external supply voltage and a load capacitance of 30 pF is described. Current-mirror/PMOS cross-coupled cascade sense amplifier circuits with a noise-immune data-latch circuit are used. A polysilicon PMOS load memory cell enables a 0.5- mu A standby current (V/sub cc/=3 V) with a 17- mu m/sup 2/ memory cell area. A 122-mm/sup 2/ (7.2*16.9-mm) chip is achieved by the double-array word-decoder architecture.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W3149260094 date "1990-01-01" @default.
- W3149260094 modified "2023-09-23" @default.
- W3149260094 title "A 23 ns 4 Mb CMOS SRAM with 0.5 mu A standby current" @default.
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- W3149260094 doi "https://doi.org/10.1109/isscc.1990.110161" @default.
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