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- W3150953732 abstract "The clock tree is the interconnect net on systems-on-chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall power dissipations are possible by optimizing the clock tree. Although these savings are already relevant at system-level, only little effort has been made to consider the clock tree at higher levels of abstraction. This paper shows how the clock-tree can be integrated into system-level power estimation and optimization. A clock tree routing algorithm is chosen, adapted to the system-level and then integrated into an algorithmic-level power optimization tool. Experimental results demonstrate the importance of the clock tree for system-level power optimization" @default.
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- W3150953732 date "2007-04-01" @default.
- W3150953732 modified "2023-09-25" @default.
- W3150953732 title "System Level Clock Tree Synthesis for Power Optimization" @default.
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- W3150953732 doi "https://doi.org/10.1109/date.2007.364543" @default.
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