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- W3152980209 abstract "With the rapid advancement of imaging technology, space-based remote sensing instruments are becoming more sophisticated and are producing substantially more amounts of data for downloading. Data alteration is very likely to occur during the transmission over the long distances from probes to carrier spacecraft and subsequently back to Earth,. Cyclic Redundancy Check (CRC) is the most well-known data package error check technique which has been used in many applications. Unfortunately, due to its serial computation process, it could be a bottleneck for critical applications that require rapid processing. To overcome such issue, we present here a parallel CRC computational method based on an FPGA with simulation and testing to validate the methodology." @default.
- W3152980209 created "2021-04-26" @default.
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- W3152980209 date "2021-04-12" @default.
- W3152980209 modified "2023-09-23" @default.
- W3152980209 title "Parallel computation of CRC-code on FPGA" @default.
- W3152980209 doi "https://doi.org/10.1117/12.2586144" @default.
- W3152980209 hasPublicationYear "2021" @default.
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