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• W3156992018 abstract "In the present study, the layout structure of an n-MOSFET, which is vulnerable to radiation, was designed in a different way to enhance its tolerance to radiation. Radiation damage assessment was conducted using modeling and simulation (M&S) techniques before actual semiconductor process fabrication and radiation tests to verify its tolerance properties. Based on the M&S techniques, the role of each layer was determined to improve the radiation tolerance of semiconductors, and the layout design of an n-MOSFET with enhanced radiation tolerance was optimized. The optimized radiation-tolerant n-MOSFET design was implemented in the 0.18-um CMOS bulk process, and radiation exposure tests were conducted on the device. A cumulative radiation dose up to 2 Mrad(Si) was applied to verify its radiation-tolerant performance. Developing new devices using M&S techniques for radiation damage assessment allows reliable estimates of their electrical and radiation-tolerant properties to be obtained in advance of the actual manufacturing process, thereby minimizing development costs and time." @default.
• W3156992018 created "2021-04-26" @default.
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• W3156992018 date "2021-04-08" @default.
• W3156992018 modified "2023-10-15" @default.
• W3156992018 title "Modeling and Simulation-Based Layout Optimization for Tolerance to TID Effect on n-MOSFET" @default.
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• W3156992018 doi "https://doi.org/10.3390/electronics10080887" @default.
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