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- W3161260555 abstract "With an increased reliance on the integrated circuits (IC), there has been a tremendous increase in the demand for the intellectual property (IP) cores by the industries, as they showcase minimal design time and high productivity. This paper delineates a novel pipe lined architecture of Euclidean Distance IP core and Squared Euclidean Distance IP core, designed to work on IEEE 754–Floating-point Single Precision Data format, with the flexibility to select a number of variables (data points) up to 65535. IP Core is designed and implemented on FPGA-Zedboard Zynq-7000, and to be used in future on FPGAs." @default.
- W3161260555 created "2021-05-24" @default.
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- W3161260555 date "2020-01-01" @default.
- W3161260555 modified "2023-09-23" @default.
- W3161260555 title "Hardware Accelerator for Squared-euclidean Distance" @default.
- W3161260555 hasPublicationYear "2020" @default.
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