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- W3162063410 abstract "With the growing demand for on-chip, low-power clock references in emerging sensor and IoT systems with extreme power limitations, performance of these frequency references requires continued improvement in energy efficiency, area, frequency stability, and frequency reconfigurability. RC oscillators using a frequency-locked loop (FLL) [1 - 6] formed by a frequency detector (FD), an error amplifier, and a voltage-controlled-oscillator (VCO) are increasingly used. Compared to a conventional RC relaxation oscillator, the absence of a PVT-sensitive comparator enhances frequency stability. The FD is the dominant FLL block for determining power, noise, and frequency stability performance of the oscillator. In [1], [2], a differential FD provides superior immunity to supply and ground noise, however these topologies lack frequency reconfigurability without changing R <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>REF</sub> and C <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>REF</sub> . In [3 - 6], the FD is implemented using a switched-capacitor and a voltage reference with resistor, where frequency can be adjusted using the reference voltage. However, voltage-domain adjustment is limited by the DC operating range, and generation of a stable, adjustable on-chip voltage reference is required." @default.
- W3162063410 created "2021-05-24" @default.
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- W3162063410 date "2021-04-01" @default.
- W3162063410 modified "2023-09-26" @default.
- W3162063410 title "A Digitally-Reconfigurable RC Frequency Generator using Impedance IQ-Balanced Frequency-Locked-Loop with Selectable Phase Mixing" @default.
- W3162063410 doi "https://doi.org/10.1109/cicc51472.2021.9431492" @default.
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