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- W3165806483 abstract "More and more attention is being paid to the use of massive parallel computing performed on many-core Networks-on-Chip (NoC) in order to accelerate performance. Simultaneously deploying multiple applications on NoC is one feasible way to achieve this. In this paper, we propose a multi-phase-based multi-application mapping approach for NoC design. Our approach began with a rectangle analysis, which offered several potential regions for application. Then we mapped all tasks of the application into these potential regions using a genetic algorithm, and identified the one which exhibited the strongest performance. When the packeted regions for each application were identified, a B*Tree-based simulated annealing algorithm was used to generate the optimal placement for the multi-application mapping regions. The experiment results show that the proposed approach can achieve a considerable reduction in network power consumption (up to 23.45%) and latency (up to 24.42%) for a given set of applications." @default.
- W3165806483 created "2021-06-07" @default.
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- W3165806483 date "2021-05-26" @default.
- W3165806483 modified "2023-10-17" @default.
- W3165806483 title "A Multi-Phase Based Multi-Application Mapping Approach for Many-Core Networks-on-Chip" @default.
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- W3165806483 doi "https://doi.org/10.3390/mi12060613" @default.
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