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- W3167604540 abstract "With continuous technology scaling, minimizing leakage power has become the prime area of concern in digital circuits. Different techniques were proposed to minimize the active leakage power in sub-micron technologies. In this paper, reduction in leakage power of 6T Static Random Access Memory (SRAM) is proposed using power gating technique. Power gating is the most effective technique to reduce the sub-threshold leakage current in the digital circuits. Initially, different analyses were done in terms of voltage scaling and sleep transistor width considering the Static Noise Margin (SNM), delay and power consumption in 6T SRAM. The analysis of power consumption was carried out with or without power gating using extensive simulation over HSPICE. The simulation results are based on the 32 nm and 45 nm Berkeley Predictive Technology Model (BPTM). The simulation results showed the effective leakage reduction and delay improvement with cell stability in memory array operation compared with the conventional 6T SRAM." @default.
- W3167604540 created "2021-06-22" @default.
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- W3167604540 date "2015-04-15" @default.
- W3167604540 modified "2023-09-24" @default.
- W3167604540 title "An Analysis of Power and Stability of 6T SRAM Using Power Gating Technique" @default.
- W3167604540 hasPublicationYear "2015" @default.
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