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- W3170522012 abstract "Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. As cutting-edge technology marches into 3nm node in next a couple of years, significant reduction of Return-On-Investment (ROI) becomes a critical issue. IRDS roadmap predicts ultimate minimum gate and metal pitch at 38 and 16nm. At 3nm, it’s expected just a few nanometer larger than this ultimate minimum geometry, although scaling factor from previous node is not even sufficient to achieve target die area scaling, 0.5~0.6X. Electrostatic control, RMG process margin, source/drain contact resistance and yield control, Middle-Of-Line (MOL) local routing parasitic RC control, and Backend-Of-Line (BEOL) metal and via resistance control are some of challenges for achieving target PPA gain. Gate-All-Around (GAA) FET can improve electrostatic control over FinFET and can provide continuous scaling path below 3nm node. Backside-Power-Distribution-Network (BS-PDN) can alleviate MOL and BEOL complexity. High-NA EUV promises reasonable mask count and patterning cost. Chiplet partition and heterogeneous integration in 2.5D and 3D can provide die size control and system level power-perf gain. Close collaboration among system architect, IP designers, and device/process engineers are needed to maximize PPA gain while minimizing cost/effort. This talk will discuss methodology and key aspect of such co-optimization collaboration." @default.
- W3170522012 created "2021-06-22" @default.
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- W3170522012 date "2021-04-19" @default.
- W3170522012 modified "2023-09-23" @default.
- W3170522012 title "Design/System Technology Co-Optimization for 3nm Node and Beyond" @default.
- W3170522012 doi "https://doi.org/10.1109/vlsi-tsa51926.2021.9440089" @default.
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