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• W3170939208 abstract "In this work, we report a detailed study and modeling of bulk current in the low forward bias region. In the forward bias region, the bulk current shows a gate-induced drain leakage (GIDL) such as strong modulation with gate voltage although from the band alignment one would not expect any tunneling current. We propose physics-based modeling of this effect and derive a compact model for circuit simulators as state-of-the-art compact models are not suitable to capture this effect. The proposed model has been validated with measurement from Intel's bulk FinFET device." @default.
• W3170939208 created "2021-06-22" @default.
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• W3170939208 date "2021-07-01" @default.
• W3170939208 modified "2023-09-30" @default.
• W3170939208 title "Anomalous GIDL Effect With Back Bias in FinFET: Physical Insights and Compact Modeling" @default.
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• W3170939208 doi "https://doi.org/10.1109/ted.2021.3083483" @default.
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