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• W3171786469 abstract "While the lateral GaN power integration technology allows integration of half-bridges, the conductive Si-substrate causes static and dynamic biasing effects. This work investigates capacitance-related effects in monolithic half-bridges on GaN-on-Si and GaN-on-SOI substrates and various feasible substrate terminations. The effect of the substrate capacitances and termination on the effective C <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>ISS</sub> , C <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>OSS</sub> , C <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>RSS</sub> device capacitances and switch-node capacitance C <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>SW</sub> , switching energy E <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>SW</sub> and gate-charge Q <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>G</sub> in half-bridges is analyzed. A gate-to-gate cross-coupling capacitance C <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>XSS</sub> in monolithic GaN-on-Si half-bridges on floating substrates is revealed. Furthermore, a small unintentional integrated dc-link capacitance C <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DC</sub> also follows from the analysis for monolithic GaN-on-Si half-bridges on floating substrate. Measurements of GaN-on-Si half-bridges with different substrate terminations verify the analysis. The analysis of the GaN-on-Si half-bridge with floating substrate shows an effectively reduced output capacitance and the best trade-off in terms of C <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>RSS</sub> increase, which is verified by measurements where it shows the highest hard-switching dc-dc efficiency of the analyzed configurations. The analysis shows how buried oxides in GaN-on-SOI half-bridges increases switch-node capacitance and thus switching losses or times. At 200 V, the efficiency of the GaN-on-Si half-bridge on floating substrate, as feasible for a monolithic half-bridge, exceeds the measured efficiency of a conventional half-bridge due to the reduced effective capacitance." @default.
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• W3171786469 date "2021-05-30" @default.
• W3171786469 modified "2023-09-27" @default.
• W3171786469 title "Investigation of GaN-on-Si and GaN-on-SOI Substrate Capacitances for Discrete and Monolithic Half-Bridges" @default.
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• W3171786469 doi "https://doi.org/10.23919/ispsd50666.2021.9452213" @default.
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