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- W3174403583 abstract "This letter details a fast and efficient implementation of the Montgomery modular multiplication by taking advantage of parallel multipliers and adders. This implementation was programmed in high-level synthesis language and tested on a field-programmable gate array device. In order to test the performance of the proposal, a sequential version of the algorithm was also implemented in hardware. Moreover, we compared the parallel implementation with a software version and with five contributions from the literature. This way, we found that our proposal improves the performance of all other implementations." @default.
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- W3174403583 date "2022-03-01" @default.
- W3174403583 modified "2023-10-18" @default.
- W3174403583 title "Fast Montgomery Modular Multiplier Using FPGAs" @default.
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- W3174403583 doi "https://doi.org/10.1109/les.2021.3090029" @default.
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