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• W3177439118 abstract "In this paper, a dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loops is proposed and analyzed. The proposed topology is based on two tuning loops: a fine-tuning loop and a coarse-tuning loop. A coarse-tuning loop is used for fast convergence, and a fine-tuning loop is used to complete fine adjustments. The proposed phased-locked loop (PLL) circuit is designed based on the TSMC 0.35-/spl mu/m 1P4M CMOS process with a 3.3-V supply voltage. HSPICE simulation shows that the lock time of the proposed PLL can be reduced over 82% in comparison to the conventional PLL. An experimental chip was implemented and measured. The measurement results show that the proposed PLL has fast locking properties." @default.
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• W3177439118 date "2003-01-01" @default.
• W3177439118 modified "2023-09-23" @default.
• W3177439118 title "A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop." @default.
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