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- W3189703952 abstract "<p indent=0mm>As a new open-source reduced instruction set architecture, RISC-V has advantages of low power consumption, small area and high performance. Therefore, technology and products based on RISC-V are developing rapidly. However, currently there are few medium and high end 64 bit CPU design instances based on the RISC-V architecture, and it is also hard to find corresponding commercial IP, especially for high-speed network applications. In this paper, we firstly improved the open source 64 bit U500 RISC-V SoC by extending the Bus width and adding L2 Cache, and etc. Secondly we implemented a complete 100 Gbps Ethernet function, which includes MAC, PCS, and SerDes, and the TX buffer and RX buffer used for the function. Finally we proved correctness and effectiveness of entire 64 bit RISC-V CPU design and 100 Gbps Ethernet function by simulation, FPGA verification and boot of Linux operation system. The designed RISC-V CPU and 100 Gbps Ethernet function can be applied to data center application such as smart network interface cards." @default.
- W3189703952 created "2021-08-16" @default.
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- W3189703952 date "2021-04-01" @default.
- W3189703952 modified "2023-10-18" @default.
- W3189703952 title "Design of RISC-V CPU for 100 Gbps Network Application" @default.
- W3189703952 doi "https://doi.org/10.3724/sp.j.1089.2021.18538" @default.
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