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- W3192772839 abstract "A technique to mitigate timing errors induced by power supply droops is featured. We propose an inverter-based droop detector as well as dual mode logic (DML) to achieve a droop-resistant timing response. The droop detector is based on capacitor ratios and is thus less sensitive to process/voltage/temperature (PVT) and to random offset than the prior art. The DML can alter its power/performance ratio based on the droop level input it receives from the detector, such that the critical timings are preserved. A prototype instantiating a demo of the scheme was fabricated in a TSMC 65 nm process, incorporating a simultaneous three-level detector and a DML-based ripple carry adder (RCA). The droop detector consumes 62 <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$mu text{W}$ </tex-math></inline-formula> , has a response time of 2 ns, and an accuracy of 0.9% of Vdd, making it one of the fastest, most accurate, and lowest power droop detectors in its class. The RCA can maintain timing for voltage droops up to 400 mV. A potential supply level reduction of up to 12% was demonstrated for the RCA, and a similar reduction could be achieved with larger-scale DML digital circuits as well." @default.
- W3192772839 created "2021-08-16" @default.
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- W3192772839 date "2022-02-01" @default.
- W3192772839 modified "2023-10-04" @default.
- W3192772839 title "A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic" @default.
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- W3192772839 doi "https://doi.org/10.1109/jssc.2021.3091586" @default.
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