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- W3193826708 abstract "In the assembly pipeline of Whole Genome Sequencing (WGS), read mapping is a widely used method to re-assemble the genome. It employs approximate string matching and dynamic programming-based algorithms on a large volume of data and associated structures, making it a computationally intensive process. Currently, the state-of-the-art data centers for genome sequencing incur substantial setup and energy costs for maintaining hardware, data storage and cooling systems. To enable low-cost genomics, we propose an energy-efficient architectural methodology for read mapping using a single system-on-chip (SoC) platform. The proposed methodology is based on the q-gram lemma and designed using a novel architecture for filtering and verification. The filtering algorithm is designed using a parallel sorted q-gram lemma based method for the first time, and it is complemented by an in-situ verification routine using parallel Myers bit-vector algorithm. We have implemented our design on the Zynq Ultrascale+ XCZU9EG MPSoC platform. It is then extensively validated using real genomic data to demonstrate up to 7.8× energy reduction and up to 13.3× less resource utilization when compared with the state-of-the-art software and hardware approaches." @default.
- W3193826708 created "2021-08-30" @default.
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- W3193826708 date "2022-09-01" @default.
- W3193826708 modified "2023-10-18" @default.
- W3193826708 title "An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification" @default.
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- W3193826708 doi "https://doi.org/10.1109/tcbb.2021.3106311" @default.
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