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- W3199544981 abstract "This article presents a multipolar neural stimulation and mixed-signal neural data acquisition (DAQ) chipset for fully implantable bi-directional brain–computer interfaces (BD-BCIs). The stimulation system employs four 40 V compliant current-stimulators, each capable of sourcing/sinking a maximum 12.75 mA stimulation current, connected to 16 output channels through a high-voltage (HV) switch fabric. A novel time-based charge balancing (TBCB) technique is introduced to reduce the residual voltage on the electrode-electrolyte interface during the inter-pulse time interval, achieving 2 mV charge balancing precision. Additionally, an analytical study of the charge balancing accuracy for the proposed technique is provided. The recording system incorporates a dual-mode DAQ architecture that consists of a 32-element front-end array and a mixed-signal back-end including analog-to-digital converters (ADCs) for both training (i.e., full-band) and decoding (i.e., baseband) operations. Leveraging the flexibility of the multipolar operation, stimulation-side contour shaping (SSCS) artifact cancellation is adopted to significantly suppress stimulation artifacts by up to 45 dB. SSCS method prevents the recording front-ends from saturation and greatly relaxes the dynamic range requirement of the recording system, enabling a truly bi-directional operation. The prototype chipset is fabricated in an HV 180-nm CMOS process and demonstrates a significant performance improvement compared to the prior art." @default.
- W3199544981 created "2021-09-27" @default.
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- W3199544981 date "2022-06-01" @default.
- W3199544981 modified "2023-10-16" @default.
- W3199544981 title "A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression" @default.
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- W3199544981 doi "https://doi.org/10.1109/jssc.2021.3108578" @default.
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