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• W3200520713 abstract "Blocking the grid voltage imbalance through the <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$alpha beta$</tex-math></inline-formula> -frame delayed signal cancellation ( <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$alpha beta$</tex-math></inline-formula> DSC) operator requires a relatively high delay value of <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$1/4$</tex-math></inline-formula> cycle. Since the dynamic behavior of the <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$alpha beta$</tex-math></inline-formula> -frame cascaded delayed signal cancellation based phase-locked loop ( <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$alpha beta$</tex-math></inline-formula> CDSC-PLL) depends on the total delay length of the cascaded operators, this value can slow down the dynamic response. In this paper, however, inspired by the delayed signal cancelation (DSC) concept, an enhanced <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$alpha beta$</tex-math></inline-formula> -frame DSC operator, which removes the grid voltage imbalance with a delay length of only <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$1/12$</tex-math></inline-formula> cycle, is proposed. The small-signal model of the suggested frequency adaptive operator is derived, making the tuning procedure and stability analysis easy yet effective. Due to the shorter delay length, using the proposed operator in the <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$alpha beta$</tex-math></inline-formula> CDSC-PLL structure leads to a higher speed-of-response and, therefore, a less phase-angle error during grid voltage scenarios. Moreover, when the total delay length decreases, the filtering capability will be improved using more operators at the chain of the cascaded DSC operators. The performance of the <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex-math notation=LaTeX>$alpha beta$</tex-math></inline-formula> CDSC-PLL and its suggested enhanced structure, benefiting from the proposed operator, are compared through theoretical analysis and experimental tests, which verify that the proposed structure offers a better dynamic response and filtering capability." @default.
• W3200520713 created "2021-09-27" @default.
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• W3200520713 date "2022-06-01" @default.
• W3200520713 modified "2023-09-27" @default.
• W3200520713 title "Dynamic Response and Filtering Capability Improvement of $alpha beta$-Frame Cascaded Delayed Signal Cancellation Based PLL" @default.
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• W3200520713 doi "https://doi.org/10.1109/tec.2021.3114317" @default.
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