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• W3203092018 abstract "It is well known that interposer-based 2.5-D integrated circuit (IC) designs have become one of the most promising solutions for providing yield improvement, enhancing system performance, decreasing power consumption, and supporting heterogeneous integration. In this article, given a set of nets including some inter-chip or through-silicon buses between chips and package, inside a silicon interposer, a via-avoidance-oriented routing algorithm can be proposed to minimize the number of the used layers by satisfying the noncrossing constraint between two nets and the constraint of using no via on the inter-chip sub-nets and no vertical detour on the through-silicon sub-nets in multiple-layer interposer routing. The routing process in our proposed algorithm can be divided into two sequential steps: iterative routing step and refinement step. In the iterative routing step, the routing process of all the given nets can be completed for layer minimization in a top-down layer-by-layer manner. In each iteration, based on the definition of the obstacle-aware routing pattern for the inter-chip sub-net on one given net, the assignment of the obstacle-aware routing patterns can be firstly obtained in single-layer routing. Furthermore, the routing paths of some inter-chip sub-nets and the partial or full routing paths of some through-silicon sub-nets can be assigned and routed onto the available layer by using a maze routing process under the detour constraints. In the refinement step, based on the routing result of the given nets on the used layers, the detoured inter-chip or through-silicon sub-nets can be firstly reassigned and rerouted for the detour reduction of the given nets. Furthermore, a set of zigzag paths can be inserted onto some nets inside the given inter-chip or through-silicon buses for skew minimization. Compared with the combination of the iterative routing using Cadence’s automatic router and the detouring-path insertion on the number of the used layers, the experimental results show that our proposed routing algorithm can use reasonable CPU time and shorter wirelength to decrease 19.3% of the number of the used layers for eight tested examples on the average." @default.
• W3203092018 created "2021-10-11" @default.
• W3203092018 creator A5071940138 @default.
• W3203092018 date "2021-11-01" @default.
• W3203092018 modified "2023-09-27" @default.
• W3203092018 title "Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs" @default.
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• W3203092018 doi "https://doi.org/10.1109/tvlsi.2021.3113918" @default.
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