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- W3204936701 abstract "The recent technological advancements has made the circuit integration to advance at an unprecedented rate. Along with it, the growing demand for long battery life devices has paved ways for new design schemes that could minimize the power consumed by electronic circuits. As everyone knows, most of the power consumed by the device is during the testing phase and another major contributor towards the dynamic power consumption is the clocking block which usually runs for the entire on-mode period of the device. A weighted pseudo random pattern generator is used for bringing down dynamic energy loss incurred by test vectors. The weighted patterns minimizes the switching between test vectors and hence the power can be brought down. The proposed design makes use of a modified clock gating technique along with weighted pseudo random pattern generator to cut down power consumed during testing phase. The proposed design was designed and simulated using Xilinx Vivado." @default.
- W3204936701 created "2021-10-11" @default.
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- W3204936701 date "2021-08-04" @default.
- W3204936701 modified "2023-09-27" @default.
- W3204936701 title "Energy Efficient Weighted Pseudo Random Pattern Generator" @default.
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- W3204936701 doi "https://doi.org/10.1109/icesc51422.2021.9532971" @default.
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