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- W3205659916 abstract "We have a FPGA design, we make it fast, efficient, and tested for a few important examples. Now we must infer a general solution to deploy in the data center. Here, we describe the FPGA DPUV3INT8 design and our compiler effort. The hand-tuned SW-HW solution for Resnet50_v1 has (close to) 2 times better images per second (throughput) than our best FPGA implementation; the compiler generalizes the hand written techniques achieving about 1.5 times better performance for the same example, the compiler generalizes the optimizations to a model zoo of networks, and it achieves 80+% HW efficiency." @default.
- W3205659916 created "2021-10-25" @default.
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- W3205659916 date "2021-10-08" @default.
- W3205659916 modified "2023-09-27" @default.
- W3205659916 title "DPUV3INT8: A Compiler View to programmable FPGA Inference Engines" @default.
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