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• W3206672274 endingPage "108189" @default.
• W3206672274 startingPage "108189" @default.
• W3206672274 abstract "The impact of negative capacitance (NC) of the ferroelectric materials in controlling the direct source to drain tunneling (DSDT) in ultra-short channel FETs is presented in this paper. Besides, an analytical model is developed by solving 2-D Poisson’s equation incorporating the degeneracy of source/drain (S/D) regions. We demonstrate that in NC gate stack based Si channel FETs (NC-FETs), the scaling limit can be pushed down to 7 nm gate length, without using effective mass engineering and alternate channel materials. However, under severe subthreshold tunneling circumstances, we find that as the % content of tunneling current rises above the value of 50% in the net current, the subthreshold slope (SS) ceases to improve with the higher ferroelectric thickness. The rigorous analysis of DSDT-Negative drain induced barrier lowering (NDIBL) and impact of the S/D doping over DSDT is also incorporated in the paper. It is found that DSDT decreases drastically in the NCFET compared to baseline FETs due to the NC effect. Hence, using NC effect, transistor can be scaled down to 7 nm physical gate length with SS < 80 mV/dec and IOFF < 70 nA/μm compared to 173 mV/dec and 1.5×106 nA/μm, respectively for the baseline FET at the same gate length." @default.
• W3206672274 created "2021-10-25" @default.
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• W3206672274 date "2021-12-01" @default.
• W3206672274 modified "2023-10-02" @default.
• W3206672274 title "Addressing source to drain tunneling in extremely scaled Si-transistors using negative capacitance" @default.
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• W3206672274 doi "https://doi.org/10.1016/j.sse.2021.108189" @default.
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