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• W3206768003 abstract "Logic synthesis is a challenging and widely-researched combinatorialoptimization problem during integrated circuit (IC) design. It transforms ahigh-level description of hardware in a programming language like Verilog intoan optimized digital circuit netlist, a network of interconnected Boolean logicgates, that implements the function. Spurred by the success of ML in solvingcombinatorial and graph problems in other domains, there is growing interest inthe design of ML-guided logic synthesis tools. Yet, there are no standarddatasets or prototypical learning tasks defined for this problem domain. Here,we describe OpenABC-D,a large-scale, labeled dataset produced by synthesizingopen source designs with a leading open-source logic synthesis tool andillustrate its use in developing, evaluating and benchmarking ML-guided logicsynthesis. OpenABC-D has intermediate and final outputs in the form of 870,000And-Inverter-Graphs (AIGs) produced from 1500 synthesis runs plus labels suchas the optimized node counts, and de-lay. We define a generic learning problemon this dataset and benchmark existing solutions for it. The codes related todataset creation and benchmark models are availableathttps://github.com/NYU-MLDA/OpenABC.git. The dataset generated is availableathttps://archive.nyu.edu/handle/2451/63311" @default.
• W3206768003 created "2021-10-25" @default.
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• W3206768003 date "2021-10-21" @default.
• W3206768003 modified "2023-09-27" @default.
• W3206768003 title "OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis." @default.
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