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- W3208532083 abstract "The standard cell power consumption reduction is one of primary goals of integrated circuit design, as the consumed power of chip has direct impact on chip lifetime and performance. There are different techniques of power consumption including power gating, low power design, voltage scaling, etc. The proposed method is aiming to power consumption reduction by standard cell sleep mode control using neural network integration. Presented enhancement methods of standard cells is inserting special addition in cells, hence giving opportunity to run the cell in sleep mode without consumpting power. Experiments show, that by using proposed method, power consumption is reduced by about 12% percent, while having increase in area by 5…28% and timing degradation by about ∼16%." @default.
- W3208532083 created "2021-11-08" @default.
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- W3208532083 date "2021-09-10" @default.
- W3208532083 modified "2023-09-26" @default.
- W3208532083 title "Standard Cell Library Enhancement Using Neural Network Based Sleep Mode Control Integration For Low Leakage Designs" @default.
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- W3208532083 doi "https://doi.org/10.1109/ewdts52692.2021.9581039" @default.
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