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- W3208704305 abstract "In the recent times, power economizing is becoming most essential factor of a circuit due to the technology scaling beyond sub-1OOnm. Besides the combinational logic, sequential logic blocks also play a major role in the design of power efficient complex computational systems. This paper introduces the Optimized GDI Technique (OGDI) for the design of sequential logic blocks. A Sequence detector is designed using OGDI technique and the performance is compared with the conventional CMOS technique. The results obtained using OGDI logic has shown significant improvement and achieved more than 28% power savings in comparison with the CMOS logic. Cadence Virtuoso is used for simulation and analysis, and 45nm technology is used." @default.
- W3208704305 created "2021-11-08" @default.
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- W3208704305 date "2021-09-24" @default.
- W3208704305 modified "2023-09-23" @default.
- W3208704305 title "Implementation of Sequence Detector using Optimized GDI Technique" @default.
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- W3208704305 doi "https://doi.org/10.1109/gucon50781.2021.9573941" @default.
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