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- W3209368512 abstract "This work is dedicated to assertion-based verification of real time logic control systems that are specified by a state diagram with state looping and implemented by hardware description language. The proposed method is based on the assertion apparatus that is used to describe the temporal nature of the timed FSM properties." @default.
- W3209368512 created "2021-11-08" @default.
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- W3209368512 date "2021-09-10" @default.
- W3209368512 modified "2023-10-17" @default.
- W3209368512 title "Assertion Based Design of Timed Finite State Machine" @default.
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- W3209368512 doi "https://doi.org/10.1109/ewdts52692.2021.9581046" @default.
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