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- W3209506799 abstract "Abstract With advancements in technology, size and speed have been the important facet in VLSI interconnects. Interconnects are known as the basic building block that provide a connection between two or more blocks and have scaling problems that an IC designer faces while designing. As scaling increases, the impact of interconnect in the VLSI circuits became even more important. It controls all the important electrical characteristics on the chip. With scale-down technology, interconnects not only become closer with each other but their dimensions also change which can directly impact the circuit parameters. Certain RC structures have already been defined to control these parameters but in this paper, authors have proposed a new interconnect structure with improved Elmore delay estimation to reduce delay and power consumption in lumped and distributed interconnect circuits using Pulse and Ramp inputs. Further, the proposed model is estimated and verified theoretically. The linear relationship of power consumption and delay for the RC structure has been observed. The proposed structure with improved Elmore delay estimation shows improvement in delay by 64.25% in lumped circuits and 68.75% in distributed circuits in comparison to existing Elmore delay calculations which help in increasing the overall speed of the interconnect circuit." @default.
- W3209506799 created "2021-11-08" @default.
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- W3209506799 date "2021-11-03" @default.
- W3209506799 modified "2023-10-16" @default.
- W3209506799 title "Novel Global Interconnect structure with improved Elmore Delay Estimation for Low-Power Applications" @default.
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- W3209506799 doi "https://doi.org/10.21203/rs.3.rs-1031810/v1" @default.
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