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- W3211700755 abstract "Lateral III–V nanowire (NW) MOSFETs are a promising candidate for high-frequency electronics. However, their circuit performance is not yet assessed. Here, we integrate lateral nanowires (LNWs) in a circuit environment and characterize the transistors and amplifiers. MOSFETs are fabricated in a simple scheme with a dc transconductance of up to 1.3 mS/ <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$mu text{m}$ </tex-math></inline-formula> , ON-resistance down to <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$265 Omega cdot mu text{m}$ </tex-math></inline-formula> , and cutoff frequencies up to 250 GHz, measured on the circuit level. The circuit model estimates 25% device parasitic capacitance increase due to back-end-of-line (BEOL) dielectric cladding. A low-noise amplifier input stage is designed with optimum network design for a noise matched input and an inductive peaking output. The input stage shows up to 4-dB gain and 2.5-dB noise figure (NF), at 60 GHz. Utilizing gate-length scaling in the circuit environment, the obtained normalized intrinsic gate capacitance value of 0.34-aF/nm gate length, per NW, corresponds well to the predicted theoretical value, demonstrating the circuit’s ability to provide intrinsic device parameters. This is the first mm-wave validation of noise models for III–V LNW MOSFETs. The results demonstrate the potential for utilization of the technology platform for low-noise applications." @default.
- W3211700755 created "2021-11-22" @default.
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- W3211700755 date "2022-02-01" @default.
- W3211700755 modified "2023-10-10" @default.
- W3211700755 title "Lateral III–V Nanowire MOSFETs in Low-Noise Amplifier Stages" @default.
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- W3211700755 doi "https://doi.org/10.1109/tmtt.2021.3124088" @default.
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