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- W3216200411 abstract "We propose a data acquisition system that enables over-sampling of signals with an external high-speed clock, to overcome the unreliability of the existing data acquisition method that uses a DRAM memory clock, when applied to data rate fifth-generation synchronous dynamic random-access memory [1]. We present a simple noise-modeling method and signal-recovery algorithm with a noise range where our algorithm behaves reliably at error rate < 10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>−6</sup> . In addition, we propose an entire data acquisition system architecture that uses a Xilinx FPGA VCU118 board." @default.
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- W3216200411 date "2021-10-06" @default.
- W3216200411 modified "2023-09-23" @default.
- W3216200411 title "Giga-sample Data Acquisition Method for High-speed DDR5 SDRAM" @default.
- W3216200411 doi "https://doi.org/10.1109/isocc53507.2021.9614030" @default.
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