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• W3217051079 abstract "Increased outsourcing of Integrated Circuit (IC) design and fabrication combined with malicious hardware security threats such as contactless optical probing have greatly decreased an attacker’s difficulty in reverse engineering or maliciously modifying a given circuit. This has become a significant concern for the safety and security of the semiconductor industry. Physical inspection techniques have been used to validate the IC hardware integrity and detect security threats to address these concerns. However, most physical inspection methods for ICs rely upon removing unwanted epoxy packaging material without damaging the device under test (DUT). Therefore, the precise removal of the IC packaging guided by knowledge of the packaging structure is very important for efficiency and accuracy in this process. Currently, IC structure analysis depends on using high-resolution X-ray computed tomography (CT), which is time-consuming and lacks the spatial resolution necessary for characterizing advanced heterogeneous packages. For hardware assurance purposes, the entire volume of a device must be analyzed with high efficacy. Additionally, various packaging and the recently adopted 2.5D and 3D advanced packages bring more challenges to meet assurance requirements. Hybrid metrology, which is the combined use of inspection methods for characterization, has the potential to address the inspection challenges for advanced packaging. In this paper, a novel hybridized inspection method utilizing nondestructive THz time-domain spectrum (THz-TDS) and X-ray CT of the IC package is used to create a digital twin (DT) of the sample. The combined characterization can be leveraged to improve the efficiency and accuracy for high quality sample preparation. Hybrid inspection paired with automated sample preparation can reduce the time and operator input needed for complete verification of a large volume of samples. In this paper, the method of generating a digital twin of the IC internal regions of interest (ROI) will be introduced. Analysis of the generated digital twin is used to optimize the material removal necessary for IC verification without damaging the ROI. This inspection and removal methodology can be automated using boundary conditions from the design information of the IC package. Hybrid inspection provides the high spatial resolution thickness and geometry information for generating an automated material removal routine. This provides access to the sample’s ROI for further FIB plasma delayering and SEM verification." @default.
• W3217051079 created "2021-12-06" @default.
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• W3217051079 date "2021-09-15" @default.
• W3217051079 modified "2023-09-27" @default.
• W3217051079 title "Digital Twin Aided IC Packaging Structure Analysis for High-quality Sample Preparation" @default.
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• W3217051079 doi "https://doi.org/10.1109/ipfa53173.2021.9617431" @default.
• W3217051079 hasPublicationYear "2021" @default.
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