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- W33446668 abstract "FPGA (Field-Programmable Gate Array) technology can provide excellent accuracy and efficiency for Chip verification, which has become the key bottleneck of SoC design. Due to the resource constraints of single FPGA chip, Multi-FPGA architecture was applied to the verification of the large scale SoC design. In recent years, a variety of Multi-FPGA verification platforms have been developed, but most of them indirectly part the SoC design on the Netlist level after the synthesis procedure. A partition method is proposed in this paper, which works directly on the RTL (Register Transfer Level) code. It presents a universal partition methodology with realistic and detailed implementation, applying a linear partition algorithm. The experiment simulation of leon3, a SoC design based on SPARC processor, runs at a speed of 8 MHz correctly, over 100,000 times faster than software simulation, 1-2 times of the BEE4 FPGA based recognizable platforms." @default.
- W33446668 created "2016-06-24" @default.
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- W33446668 date "2014-01-01" @default.
- W33446668 modified "2023-09-27" @default.
- W33446668 title "A Partition Method of SoC Design Serving the Multi-FPGA Verification Platform" @default.
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- W33446668 doi "https://doi.org/10.1007/978-3-662-44491-7_4" @default.
- W33446668 hasPublicationYear "2014" @default.
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