Matches in SemOpenAlex for { <https://semopenalex.org/work/W363676365> ?p ?o ?g. }
- W363676365 abstract "Much of the chip area and power in a modern processor are used by mechanisms that compensate for slow main memory such as caches, out-of-order execution and prefetching. We attack this problem by utilizing a DRAM macro made by Hwang et. al that is faster than conventional DRAM macros, but does not conserve data in the DRAM cells after reading. Their prototype included a large write-back buffer for conserving data without degrading performance of read accesses. We eliminate this buffer by utilizing the already existing cache in processor designs at the cost of potential memory bank congestion. Two implementable and one theoretic upper-bound scheme for cache write-back are evaluated. We find that the size of the cache can be highly reduced without degrading performance when utilizing destructive-read DRAM. The large write-back buffer can be omitted when destructive-read DRAM is used with a processor with cache without significant degradation of performance." @default.
- W363676365 created "2016-06-24" @default.
- W363676365 creator A5077149313 @default.
- W363676365 date "2010-01-01" @default.
- W363676365 modified "2023-09-27" @default.
- W363676365 title "Reducing Memory Latency by Improving Resource Utilization" @default.
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