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- W37005588 abstract "BIPS-0 is a fully-integrated bipolar processor chip with 100K ECL compatible inputs and outputs. Its external clock rate is about 100 MHz, with an on-chip clock rate of about 300 MHz. The BIPS-0 chip is packaged in a 504 pin plastic pin grid array (PPGA) which provides 5 power planes, and two stripline signal layers designed to offer 348 signal lines with a characteristic impedance of 50 Ω. The chip’s signal input pads include 50 Ω termination resistors. In a system, the BIPS-0 package may be placed in a standard 504 pin zero insertion force (ZIF) socket which is soldered into a standard printed circuit board. Using Time Domain Reflectometry (TDR) and Time Domain Transmission (TDT) techniques, the package trace impedance, impedance discontinuities due to the pins and bond wires, termination resistor resistance, signal edge rates, signal quality, crosstalk, and the performance degradation due to the ZIF socket were investigated. The results of this investigation will be used in the design of the package for BIPS-1 which will have an external clock rate of about 200 Mhz. Copyright 1992 Digital Equipment Corporation d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA" @default.
- W37005588 created "2016-06-24" @default.
- W37005588 creator A5005772711 @default.
- W37005588 date "1999-01-01" @default.
- W37005588 modified "2023-09-27" @default.
- W37005588 title "Electrical Evaluation Of The BIPS-0 Package" @default.
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