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• W39721854 abstract "CMOS scaling over the years has brought great improvements in the computational speed, density and cost of microprocessors. However, scaling is approaching its limits owing to the difficulty in reducing the supply voltage with conventional MOSFETs having at best a subthreshold swing of 60mv/decade. A possible alternative is Tunnel FETs (TFETs) where carrier transport happens through band-to-band tunneling as opposed to thermal injection in MOSFETs. While silicon and III-V semiconductors have been investigated in this context, carbon-based and the large family of transition metal dichalcogenides offer more material flexibility and better electrostatic control. Bilayer Graphene (BLG) has the interesting property that an appreciable band gap can be induced electrostatically. Additionally, its low effective mass (0.05me), direct bandgap and ultra-thin body make it highly suitable for TFETs. Theoretical studies for BLG TFETs have shown promising results, although practical implementation requires several technical hurdles to be overcome. To address some of these, process modules for realization of BLG TFET have been developed in this dissertation. Channel-Length Scaling: To replace conventional Si MOSFETs, graphene and other 2D materials should demonstrate superior behavior in the short-channel devices. Thus, a recipe for fabricating devices with a channel length down to 40nm was developed and demonstrated in the lab. Also, MoS2 devices were fabricated with this recipe and their electrical properties were compared over a range of channel-lengths. Contact-doping on Single-Layer Graphene (SLG): BLG TFET architectures exploiting the effect of charge transfer between metal and graphene to realize abrupt P-i-N structure has been proposed in literature. An experimental study towards quantifying doping by metal on large area SLG was performed with Transfer Length method (TLM). Coupled with the scaling module, CVD graphene was used to obtain a statistical variation of various electrical parameters crucial for realization of logic devices. Also, an evaluation using a model based on Landauer-Buttiker formalism was performed to understand the electrostatic and geometric factors for designing P-N junctions. Further, suggestions regarding extending the results to BLG has been proposed. Gate-Stack on Graphene: Gate-dielectric scaling is very important for enabling overall device scaling. Due to weak Vander Waals’ interaction between graphene layers, growing a reliable oxide on graphene channel has been a challenge. In this work, a low temperature Atomic Layer Deposition (ALD) recipe for high k-dielectrics - Aluminum oxide (Al2O3) - over graphene has been developed and investigated through physical and electrical characterization." @default.
• W39721854 created "2016-06-24" @default.
• W39721854 creator A5055896171 @default.
• W39721854 date "2014-09-19" @default.
• W39721854 modified "2023-09-28" @default.
• W39721854 title "Process Integration for Graphene Tunnel Field Effect Transistors" @default.
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• W39721854 hasPublicationYear "2014" @default.
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