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- W41470869 abstract "Test generation procedures for large VLSI designs are required to achieve close to 100% fault coverage using a small number of tests. They also must accommodate on-chip test compression circuits which are widely used in modern designs. To obtain test sets with small sizes one could use extra hardware such as test points or use software techniques. An important aspects impacting test generation is the number of specified positions, which facilitate the encoding of test cubes when using test compression logic. Fortuitous detection or generation of tests such that they facilitate detection of yet not targeted faults, is also an important goal for test generation procedures. At first, we consider the generation of compact test sets for designs using onchip test compression logic. We introduce two new measures to guide automatic test generation procedures (ATPGs) to balance between these two contradictory requirements of fortuitous detection and number of specifications. One of the new measures is meant to facilitate detection of yet undetected faults, and the value of the measures is periodically updated. The second measure reduces the number of specified positions, which is crucial when using high compression. Additionally, we introduce a way to randomly choose between the two measures. We also propose an ATPG methodology tailored for BIST ready designs with X-bounding logic and test points. X-bounding and test points used to have a significant impact on test data compression by reducing the number of specified positions." @default.
- W41470869 created "2016-06-24" @default.
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- W41470869 date "2018-11-29" @default.
- W41470869 modified "2023-09-25" @default.
- W41470869 title "Generation of compact test sets and a design for the generation of tests with low switching activity" @default.
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- W41470869 doi "https://doi.org/10.17077/etd.93exb2ob" @default.
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