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- W416583539 abstract "For decades, memory controllers for DDRx memory exploit row-buffer locality to improve the efficiency of memory access. Recently, the bankgroup feature of the latest DDR4 memory requires inter-bankgroup parallelism to saturate the memory bus unlike previous DDRx generations. To exploit both the row-buffer locality and the interbankgroup parallelism, the DDR4 memories require intelligent memory controllers. Modern memory controllers reorder both read requests and write requests to maximize the available memory bandwidth. Compared with read requests, write requests have large scheduling space because write requests do not stall the processor pipeline unlike read requests. Therefore, several memory scheduling techniques utilize the dirty data on the last-level caches to exploit the row-buffer locality. However, these techniques cannot utilize the inter-bankgroup parallelism effectively. To maximize the memory access efficiency on the DDR4 memory access, we propose Triple-helix Writeback. Triple helix writeback analyzes the writeback request for the last-level cache to detect multiple writeback streams to utilize the inter-bankgroup parallelism. When multiple writeback streams for different bankgroups are detected, the memory controller eagerly writes the dirty data on the detected writeback streams simultaneously. This scheduled writeback method improves the memory bus utilization efficiency of complicated DDR4 memories because the memory controller can effectively exploit both the row-buffer locality and the inter-bankgroup parallelism. We evaluated Triple-helix Writeback by the cycle-accurate full system simulation. The simulation result shows that the Triple-helix Writeback improves performance and energy efficiency by 4.7% and 5.9%, respectively." @default.
- W416583539 created "2016-06-24" @default.
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- W416583539 date "2013-07-24" @default.
- W416583539 modified "2023-10-03" @default.
- W416583539 title "Triple-helix Writeback: Reducing Inner-Bankgroup Contention in DDR4 SDRAM Memory System" @default.
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