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• W4200318003 abstract "Small Delay Faults (SDFs) due to defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is in the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its behavioral features are affected by several masking impacts of the rest of the circuit. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defect devices without a major impact on yield." @default.
• W4200318003 created "2021-12-31" @default.
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• W4200318003 creator A5078514187 @default.
• W4200318003 date "2021-10-27" @default.
• W4200318003 modified "2023-09-23" @default.
• W4200318003 title "Resistive Open Defect Classification of Embedded Cells under Variations" @default.
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• W4200318003 doi "https://doi.org/10.1109/lats53581.2021.9651857" @default.
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