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- W4200370870 abstract "The ordered statistic decoding (OSD) approach for short-length BCH codes has been continuously considered as one of the promising error-correction codes by achieving a block error rate (BLER) of less than $10^{-6}$, which is attractive to the ultra-reliable and low-latency communication (URLLC) for industrial IoT (IIOT) solutions [1], [2]. However, it is hard to directly realize the conventional OSD algorithm because of the compute-intensive Gaussian elimination and iterative reprocessing steps. Based on the recent segmentation discarding decoding (SDD) approach [3], in this work, we newly present an ultralow-latency OSD architecture reducing the decoding latency by 12 times, which is implemented at an FPGA-based verification platform." @default.
- W4200370870 created "2021-12-31" @default.
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- W4200370870 date "2021-11-07" @default.
- W4200370870 modified "2023-09-25" @default.
- W4200370870 title "FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks" @default.
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- W4200370870 doi "https://doi.org/10.1109/a-sscc53895.2021.9634714" @default.
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