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- W4200498577 abstract "This paper presents a comparison of array-level performance of non-volatile SOT-MRAM and SOTFET-RAM to conventional 6T CMOS SRAM using a specially developed simulation suite that merges physics-based compact models and layout-based parasitic extraction. Unlike prior work, our characterization framework generates a full layout of the memory array including all peripheral logic and routing. The framework uses an industry-standard parasitic extraction tool to generate the full netlist including parasitics which is then simulated using compact models for the appropriate emerging non-volatile device. Using this framework, we show about 1.8x energy savings for total read operations and write operations, and 2x area savings for the SOT-based memories relative to a comparable CMOS SRAM for a <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$256times 128$</tex> array size. Our unique full-layout approach also enables important insights that challenge conventional wisdom based on higher-level modeling." @default.
- W4200498577 created "2021-12-31" @default.
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- W4200498577 date "2021-09-13" @default.
- W4200498577 modified "2023-10-16" @default.
- W4200498577 title "Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM" @default.
- W4200498577 doi "https://doi.org/10.1109/essderc53440.2021.9631814" @default.
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