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- W4205751875 abstract "This brief proposes a fully dynamic discrete-time <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>${Delta }{Sigma }$ </tex-math></inline-formula> ADC using closed-loop two-stage cascoded floating inverter amplifiers (FIA). The proposed FIA uses a non-cascoded FIA as the <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$1^{mathrm{ st}}$ </tex-math></inline-formula> stage and a cascoded one as the 2 <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$^{mathrm{ nd}}$ </tex-math></inline-formula> . By using this arrangement as well as applying metal-insulator-metal (MIM) capacitors for floating reservoir capacitors, it stably achieves high gain even with the input common-mode voltage fluctuation without an additional CMFB nor calibrations. The proposed ADC fabricated in a 65nm standard CMOS process realizes a fully dynamic operation without calibration and achieves 88.5dB SNDR, 97.9dB SFDR with an OSR of 256. It consumes 43.5 <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>${mu }text{W}$ </tex-math></inline-formula> from a 1V supply at a 10MHz sampling frequency." @default.
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- W4205751875 date "2022-03-01" @default.
- W4205751875 modified "2023-10-17" @default.
- W4205751875 title "Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers" @default.
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- W4205751875 doi "https://doi.org/10.1109/tcsii.2021.3134963" @default.
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