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- W4205918413 abstract "Multiplication operation is the core of many techniques like convolution, correlation, fast fourier transform etc. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. Optimising multiplier (in terms of delay or area or power) will have a huge impact on system performance. One of the methods adopted to reduce delay is the use of Vedic Multiplier based on “Vedic Mathematics Sutras”. In this project “Urdhava - Tiryakbhayam” Sutra is used to perform multiplication and is simulated and implemented in Xilinx ISE Design 14.7" @default.
- W4205918413 created "2022-01-26" @default.
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- W4205918413 date "2021-12-10" @default.
- W4205918413 modified "2023-09-27" @default.
- W4205918413 title "High Speed Sixty Four Bit Vedic Multiplier" @default.
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- W4205918413 doi "https://doi.org/10.1109/cict53865.2020.9672441" @default.
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