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- W4206223829 abstract "In this letter, we propose the variation-tolerant capacitive binarized neural network using the capacitance of 2-terminal MANOS memory devices. The capacitance-voltage characteristic of the synaptic device is shifted by program or erase operation. Two saturated regions of <italic xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>the C-V</i> curve are used for representing the weight of the binarized neural network (BNN), 1 and −1. Thus, the capacitance variation of the proposed synaptic device is much less than the conductance variation of the conventional synaptic devices. The effects of <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>${V}_{text {th}}$ </tex-math></inline-formula> variation and memory window on accuracy are analyzed with CIFAR10 datasets. Our simulation result shows that the proposed capacitance-based BNN is much more robust to <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>${V}_{text {th}}$ </tex-math></inline-formula> variation compared to the conductance-based BNN." @default.
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- W4206223829 date "2022-03-01" @default.
- W4206223829 modified "2023-10-17" @default.
- W4206223829 title "Variation-Tolerant Capacitive Array for Binarized Neural Network" @default.
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- W4206223829 doi "https://doi.org/10.1109/led.2022.3143140" @default.
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