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W4207015247 abstract "The reliability of SiC MOSFETs under harsh operating conditions, such as short circuit (SC) stress, remains a major concern. In this article, a dedicated aging platform is developed to study the degradation of SiC planar- and trench-gate MOSFETs under repetitive SC conditions. The static characteristics of the devices are monitored in real-time during the test. Depending on the gate bias used in the experiments, a bidirectional <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>${V}_{text {TH}}$ </tex-math></inline-formula> shift in both types of devices is observed, yet with a different degradation rate. The underlying degradation mechanisms investigated by device simulation reveal that the damaged region in the SiC planar-gate MOSFET is located near the channel area, while at the trench corner in the SiC trench-gate MOSFET. These research outcomes enable better understanding of the degradation mechanisms of different SiC MOSFET structures and possible ruggedness improvements in the future." @default.
W4207015247 created "2022-01-26" @default.
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W4207015247 date "2022-05-01" @default.
W4207015247 modified "2023-10-16" @default.
W4207015247 title "Gate Bias Dependence of <i>V</i> <sub>TH</sub> Degradation in Planar and Trench SiC MOSFETs Under Repetitive Short Circuit Tests" @default.
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W4207015247 doi "https://doi.org/10.1109/ted.2022.3142237" @default.
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