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• W4207074682 abstract "This work presents a low-jitter and low-spur, fractional- <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$N$ </tex-math></inline-formula> ring-oscillator-based digital phase-locked loop (RO-DPLL). First, to suppress fractional spurs, the probability-density-shaping delta–sigma modulator (PDS- <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$Delta Sigma text{M}$ </tex-math></inline-formula> ) is presented. Since the output codes of the PDS- <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$Delta Sigma text{M}$ </tex-math></inline-formula> are designed to have a time-invariant probability density function (PDF), they have spur immunity to any nonlinearity (NL) of the digital-to-time converter (DTC). In addition, by using a special dither consisting of uniform random numbers (URNs) based on the dithered quantization theorems, the PDS- <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$Delta Sigma text{M}$ </tex-math></inline-formula> can also suppress fractional spurs due to the NL of other loop-building circuits. Second, the DTC’s second-/third-order nonlinearity cancellation (DST-NLC) technique is presented to reduce the quantization noise (Q-noise), thereby reducing the rms jitter. The proposed RO-DPLL was fabricated in 65-nm CMOS, and it used a 0.146-mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> silicon area and 9.27-mW power. At a near-integer- <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$N$ </tex-math></inline-formula> frequency, i.e., near 5.3 GHz, the measured rms jitter and the fractional spur were less than 365 fs and −63 dBc, respectively." @default.
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• W4207074682 date "2022-09-01" @default.
• W4207074682 modified "2023-09-27" @default.
• W4207074682 title "A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-<i>N</i> Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM" @default.
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• W4207074682 doi "https://doi.org/10.1109/jssc.2022.3141782" @default.
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