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- W4210754161 abstract "A unique method has been proposed which incorporates algorithms as an alternative tool for achieving an optimized structure of $deltamathrm{p}^{+}$ Si-Ge gate-drain underlap n-TFET. The main goal is to minimize the computational cost and complexity for obtaining optimized device dimension by using several high performance meta-heuristic algorithms. The approach presented utilizes electric field expression as an objective function. The dimensions of the various sections such as the length of delta doped layer, channel, device thickness and oxide thickness which significantly affects device performance are considered as the design variables. The device is then designed and validated in Technology Computer Aided Design (TCAD) with dimensions obtained by the usage of algorithms. The ON-current, OFF-current, electric fields are found according to ITRS requirement. The best solution is provided by the human behaviour particle swarm algorithm (HBPSO). This algorithm-based technique to achieve the optimum device structure opens a new dimension in tunnel field effect transistor design. The optimised device reports an On-current of $4.5times 10^{-4}mathrm{~A}$ and OFF-current of $4.5times 10^{-12}mathrm{~A}$." @default.
- W4210754161 created "2022-02-08" @default.
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- W4210754161 date "2021-12-19" @default.
- W4210754161 modified "2023-10-18" @default.
- W4210754161 title "A meta-heuristic algorithm-based optimization δp⁺ Si-Ge gate–drain under-lap n-TFET" @default.
- W4210754161 doi "https://doi.org/10.1109/indicon52576.2021.9691589" @default.
- W4210754161 hasPublicationYear "2021" @default.
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