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- W4214655995 abstract "As memory capacity has outstripped TLB coverage, large data applications suffer from frequent page table walks. We investigate two complementary techniques for addressing this cost: reducing the number of accesses required and reducing the latency of each access. The first approach is accomplished by opportunistically flattening the page table: merging two levels of traditional 4 KB page table nodes into a single 2 MB node, thereby reducing the table's depth and the number of indirections required to traverse it. The second is accomplished by biasing the cache replacement algorithm to keep page table entries during periods of high TLB miss rates, as these periods also see high data miss rates and are therefore more likely to benefit from having the smaller page table in the cache than to suffer from increased data cache misses." @default.
- W4214655995 created "2022-03-02" @default.
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- W4214655995 date "2022-02-22" @default.
- W4214655995 modified "2023-09-23" @default.
- W4214655995 title "Every walk’s a hit: making page walks single-access cache hits" @default.
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- W4214655995 doi "https://doi.org/10.1145/3503222.3507718" @default.
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