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- W4214852049 abstract "This manuscript introduces a low-power mixed-signal foreground calibration algorithm of a pipeline analog-to-digital converter (ADC) using a digitally controlled reconfigurable switched-capacitor multiplying digital-to-analog converter (MDAC) gain controller. The proposed calibration technique forces the front-end stage MDAC gain toward its ideal value to achieve the ideal ADC output linearity. In this brief, a feedback mechanism has been employed to nullify the effect of change in MDAC gain from its ideal value by sensing a digital back-end unit response. The proposed method has been simulated using a 0.18- <inline-formula xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex-math notation=LaTeX>$mu text{m}$ </tex-math></inline-formula> CMOS process. An 11-bit pipeline ADC with a 1.5-bit stage followed by a ten bit linear back-end ADC (BE-ADC) has been used to calibrate the non-linearity of the said 1.5-bit stage. Using a low amplifier gain value of 28 dB, the signal-to-noise-and-distortion ratio (SNDR) of the ADC improves from 46.21-dB pre-calibration to 65.13-dB post-calibration." @default.
- W4214852049 created "2022-03-05" @default.
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- W4214852049 date "2022-05-01" @default.
- W4214852049 modified "2023-10-09" @default.
- W4214852049 title "A Self-Calibration Method of a Pipeline ADC Based on Dynamic Capacitance Allotment" @default.
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- W4214852049 doi "https://doi.org/10.1109/tvlsi.2022.3151479" @default.
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