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- W4214857950 abstract "In this paper, an asymmetrical Multilevel Inverter (MLI) topology with two different source configurations have been explained. The proposed topology contains 8-unidirectional switches, 1-Bidirectional Switch (BS) and 2-dc sources. Here, BS is connected in common emitter configuration mode thereby requirement of gate driver circuit become only one. The topology is nothing but cascade connection of one H-Bridge inverter and five level T -type inverter. It provides less per unit Total Standing Voltage (TSV) and it is one of the significant factor for cost requirement of semiconductor devices. Basically, the reduction of switch count indicates respective reduction in gate driver circuit, heat sink and protection circuits. The Unipolar Phase Disposition (UPD) Pulse Width Modulation (PWM) technique has been applied to the proposed topology and this technique reduces the number of carrier count as compared with conventional PD technique thereby control complexity further decreases. By taking 1:4 source configuration, it is possible to generate Ll-level output and similarly with 1:2 source configuration, it is possible to generate 7-level output using UPD technique. With step change in Modulation Index (MI) values, the performance of an inverter in both configurations have been explained. Finally, the operation of an inverter with UPD technique has been validated through MATLAB/Simulink platform." @default.
- W4214857950 created "2022-03-05" @default.
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- W4214857950 date "2021-11-01" @default.
- W4214857950 modified "2023-10-16" @default.
- W4214857950 title "A Unipolar Phase Disposition Pulse Width Modulation Technique for an Asymmetrical Multilevel Inverter Topology" @default.
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- W4214857950 doi "https://doi.org/10.1109/icissgt52025.2021.00041" @default.
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