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• W4221078264 endingPage "102485" @default.
• W4221078264 startingPage "102485" @default.
• W4221078264 abstract "Wireless network-on-chip (WNoC, a.k.a. WiNoC) architectures, as an emerging and viable alternative approach, overcome the communication constraints and drawbacks of network-on-chip (NoC) architectures. High scalability, high bandwidth, and low latency are the advantages of WNoCs that considerably alleviate the shortage of wired on-chip networks. Despite the great merits of WNoC, on the other hand, power-hungry wireless components cause problems regarding power consumption and temperature issues. Therefore, a significant challenge and an integral part of designing an efficient WNoC architecture would be resolving power management difficulties. Hence, the researchers have investigated various approaches to reduce and manage energy problems of WNoC structures while keeping up a trade-off between power efficiency and improving other performance parameters. This article presents a comprehensive systematic analysis on energy saving techniques in WNoCs. The goal is to classify state-of-the-art WNoCs architectures employing different approaches for reducing power consumption such as power gating, dynamic frequency/voltage scaling, enhancing transceiver structure, modifying topology and routing strategies. Some researchers investigate the impact of a wave-guiding medium type or wireless devices (e.g., transceivers) on power consumption. Besides, the voltage and frequency scaling, structure, routing and communication strategies are principal targets of energy efficiency." @default.
• W4221078264 created "2022-04-03" @default.
• W4221078264 creator A5013389284 @default.
• W4221078264 creator A5068176939 @default.
• W4221078264 date "2022-05-01" @default.
• W4221078264 modified "2023-10-16" @default.
• W4221078264 title "A systematic analysis of power saving techniques for wireless network-on-chip architectures" @default.
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